FIG. 1 depicts a display system 100 which may be part of a computer system. The display system 100 includes an address generator 112 which receives the PIX CK (pixel clock), HSYNC, and VSYNC signals as inputs and outputs the address of pixels of an image frame to a frame buffer 114. The frame buffer 114 typically includes one or more VRAMs for storing the pixel data of the frames. The frame buffer 114 outputs each addressed pixel from a serial port 115 thereof to a display device 116 such as a CRT or LCD. In addition, a control device 118, such as a CPU, can access the pixels of the frames in the frame buffer 114 via a random access port 113 thereof.
FIG. 2 depicts a frame 120 and a display screen 122 of the display device 116 (FIG. 1) for displaying the frame. The display screen 122 is organized into a number of horizontal scan-lines and a number of vertical scan-columns of pixels. Likewise, each frame 120 is organized into a number of horizontal frame-rows and vertical frame-columns of pixel data.
The pixels of each frame-row of the frame 120 are typically displayed on a corresponding scan-line of the display screen 122 in a raster-like fashion from left to right and from top to bottom. For example, in a display scheme called "non-interlace", the 0.sup.th frame-row of pixels is displayed on the 0.sup.th scan-line, followed by the display of the 1.sup.st frame-row on the 1.sup.st scan-line, etc. until the last frame-row is displayed on the last scan-line. In an alternative display scheme called "interlace," each frame is divided into P fields where a p.sup.th frame (where 1.ltoreq.p.ltoreq.P) contains the p-1, p-1+P, p-1+2P, p-1+3P, . . . frame-rows. In an interlace display scheme, a frame is displayed by alternately displaying each field. For example, if P=2, then frame-rows 0,2,4,6, . . . form a first field called the even field and frame-rows 1,3,5,7, . . . form a second field called the odd field. The even field is first displayed, i.e., the 0.sup.th frame-row is displayed on the 0.sup.th scan-line, followed by the display of the 2.sup.nd frame-row on the 2.sup.nd scan-line, followed by the display of the 4.sup.th frame-row on the 4.sup.th scan-line, etc. Then the odd field is displayed, i.e., the 1.sup.st frame-row is displayed on the 1.sup.st scan-line followed by the display of the 3.sup.rd frame-row on the 3.sup.rd scan-line, etc.
Often, it is desirable to scale-down or shrink the frames in the horizontal direction, the vertical direction, or both. Some systems can only scale a frame by a fixed, non-selectible scaling factor while other systems can scale a frame by a selectible scaling factor. The latter systems provide greater flexibility for use in a variety of applications.
The scaling process may be viewed as two steps. First, the number of pixels or rows are selectively reduced in the scaled direction according to a scaling factor. Then, the remaining pixels or frame-rows are merged together.
An averaging method for reducing pixels is illustrated in FIG. 3. As shown in FIG. 3, a frame may be easily scaled in the horizontal direction for either interlaced or non-interlaced displays. For example, to scale an image by I=5/6, the pixels in every 6.sup.th frame-column are discarded. The remaining pixels are then consecutively renumbered in order so that the resulting frame is contiguous.
Similarly, as shown in FIG. 4, a non-interlaced frame can be scaled by the scaling factor J in the vertical direction by periodically discarding frame-rows. For instance, a circuit may be provided which receives the HSYNC signal and periodically discards a frame-row every N HSYNC pulses. If J=1/2 then a frame-row is discarded every N=2 HSYNC pulses or every other frame-row, i.e., frame-rows 1,3,5,7, . . . are discarded. The remaining frame-rows 0,2,4,6,8 may be displayed on consecutive scan-lines 0,1,2,3,4, . . . of the display device.
Advantageously, the horizontal and vertical scaling processes are performed in real time as the frame-rows of the frame are scanned for display. However, the real-time averaging method for reducing frame-rows in a real-time vertical scaling process produces disadvantageous results in an interlace display. For example, FIG. 5 illustrates a real-time averaging method for scaling an interlace image with P=2 fields by a scaling factor of J=1/2. As shown, every other frame-row is discarded during the display of each field. Thus, during the display of the even field, the frame-rows 2,6,10,14, . . . are discarded and during the display of the odd field the frame-rows 3,7,11,15 are discarded. Thus, the frame-rows 0,1,4,5,8,9,12,13, . . . are displayed on scan-lines 0,1,2,3,4,5,6,7, . . . of the display device. However, because consecutive adjacent frame-rows are discarded, i.e., 2-3, 6-7, 10-11, etc., the resulting image displayed on the display device has annoying discontinuities.
FIG. 6 shows a conventional circuit disclosed in U.S. Pat. No. 5,025,315 which overcomes this problem. Consider the case where P=2 fields are alternately displayed. The circuit has a two-phase clock generator 15 for generating two successive clock pulses for each HSYNC pulse. The first clock pulse corresponds to the frame-row currently being scanned while the second clock pulse corresponds to the very next frame-row. The clock pulses are fed to a modulo N counter 20 which outputs a signal indicating whether or not to discard the corresponding frame-row. The outputted indication for each clock is stored in a separate circuit FF4 or FF5. The indication stored in the circuit FF4 corresponds to the currently scanned frame-row and the indication stored in the circuit FF5 corresponds to the next consecutive frame-row of the frame (which is part of the other field that is not 5 currently scanned). For example, as shown in FIG. 7, during the scan of the even field, at the HSYNC pulse of the frame-row 0, indications of whether or not to discard the frame-rows 0 and 1 are stored in the circuits FF4, FF5, respectively. At the HSYNC pulse for the frame-row 2, indications of whether or not to discard the frame-rows 2 and 3 are stored in the circuits FF4 and FF5, respectively. Likewise, at the HSYNC pulse for the frame row 4, indications of whether or not to discard the frame-rows 4 and 5, are stored in the circuits FF4 and FF5, respectively, etc. The modulo N counter 20 outputs a discard indication every N.sup.th clock pulse, i.e., every N.sup.th frame-row. On every other clock pulse, the module N counter 20 outputs a retain indication.
If the current frame-row is retained, it is stored in the frame buffer at the frame-row address pointed to by a row address counter 35 (FIG. 6) and a logic circuit 30 (FIG. 6) increments the row address counter 35 (FIG. 6) by one. If the current frame-row and the next frame row are retained, the current frame-row is stored in the frame buffer and the logic circuit 30 (FIG. 6) increments the row address counter 35 (FIG. 6) by two. This leaves a blank storage space in the frame buffer for storing the next frame-row when its field is scanned. Likewise, if the current frame-row is discarded but the next frame-row is retained, nothing is stored in the buffer. However, the logic circuit 30 (FIG. 6) increments the row address counter 35 (FIG. 6) so as to leave a blank storage space for storing the next frame-row during the scan of its field. Lastly, if both the current frame-row and the next frame-row are discarded, then nothing is stored in the frame buffer and the logic circuit 30 (FIG. 6) does not increment the row address counter 35 (FIG. 6).
When the next field is displayed, the row address counter 35 is reset to point to the first of the blank spaces left for storing frame-rows. Thereafter, the above process is repeated for the other field. For example, as shown in FIG. 7, during the scan of the odd field, the circuit determines at the HSYNC pulse corresponding to the frame-row 1 whether or not to discard the frame-rows 1 and 2, at the HSYNC pulse corresponding to the frame-row 3 whether or not to discard the frame-rows 3 and 4, etc. In response to these determinations, the row address counter 35 (FIG. 6) is incremented so that the frame-rows of the odd field are stored in the aforementioned blank spaces in the frame buffer created during the scan of the even field.
The prior art circuit is disadvantageous in that it is complex and requires complex circuitry. This relates to the complexity of the real-time averaging process in the frame reduction step. The prior art real-time averaging process requires maintaining a count of the frame-columns (in horizontal scaling) or frame-rows in (vertical scaling). The determination of whether to discard or retain pixels of frame-rows depends on this running count. Thus, each determination depends on the previous determination and hence, all determinations must be done serially, i.e., sequentially. This complicates the real-time scaling process of P field interlace frames because during the scan of each frame-row of each field, the merge process must allocate space for the next P-1 frame-rows of the other, non-displayed fields. Thus, the merge process is delayed until the reduction step is serially performed on each of the P frame-rows examained during the scan of each frame-row. As a result, the merge step is greatly complicated and encumbered. The net result is that both the reduction and merge steps consume much time and effort, and require complex circuitry.
It is therefore an object of the present invention to overcome the disadvantages of the prior art.